The fabrication of Very-Large Scale Integrated (VLSI) or Ultra-Large Scale Integrated circuit (ULSI) requires metallic wiring that connects individual devices in a semiconductor chip, to one another. One method of creating this wiring network on such small scale is a dual damascene (DD) process. In a typical DD process, an interlayer dielectric (ILD) typically comprising two dielectric layers (e.g., a via level dielectric and a line level dielectric) is formed on a substrate. In general, the via and line level dielectrics can be made of the same or different insulating films and in the former case applied as a single monolithic layer. A hard mask layer is optionally employed to facilitate etch selectivity and to serve as a polish stop. The wiring interconnect network consists of two types of features: line features that traverse a distance across the chip, and via features which connect lines in different levels together. Historically, both dielectric layers are made from an inorganic glass like silicon dioxide (SiO2) or a fluorinated silica film deposited by plasma enhanced chemical vapor deposition (PECVD).
In the dual damascene process, the position of the lines and the vias are defined lithographically in different photoresist layers and transferred into the hard mask and ILD layers using reactive ion etching processes. In one embodiment, the process sequence is a line-first approach because the trench that will house the line feature is etched first. After the trench formation, lithography is used to define a via pattern into one of the photoresist layers which is then transferred into the dielectric material to generate a via opening.
Next, the dual damascene structure is coated with a conducting liner material or material stack that serves to protect the conductor metal lines and vias and serve as an adhesion layer between the conductor and the ILD. This recess is then filled with a conducting fill material over the surface of the patterned dielectrics. The fill is most commonly accomplished by electroplating of copper, Cu, although other methods such as chemical vapor deposition (CVD) and other materials such as aluminum, Al, or gold, Au, can also be used. The fill and liner materials are then chemically mechanically polished (CMP) to be coplanar with the surface of the hard mask. A capping material is deposited over the metal or as a blanket film to passivate the exposed metal surface and to serve as a diffusion barrier between the metal and any additional ILD layers to be deposited over the interconnect structure. Silicon nitride, silicon carbide, and silicon carbonitride films deposited by PECVD are typically used as the capping material. This process sequence is repeated for each level of the interconnects on the device. Since two interconnect features are defined to form a conductor in-lay within an insulator by a single polish step, this process is designated a dual damascene process.
As with any circuit, semiconductor chips are prone to signal propagation delays which depend on the product of the line resistance, R, and the interconnect capacitance C. In order to improve the performance of semiconductor chips, manufacturers have reduced the resistivity of the metal used in fabrication by replacing Al wiring with Cu. Moreover by moving to lower dielectric constant (k) materials, manufacturers have also begun to reduce the capacitance, C, in the circuit.
The common terminology used to describe dielectric films in the semiconductor industry is to classify them as standard k (4.5<k<10), low k (k<3.0), ultra low k (2.0<k<2.5) and extreme low k (k<2.0). Ultra low k and extreme low k dielectrics generally tend to be porous with intentionally engineered voids in their structure. Since the lowest dielectric constant possible is defined by air or vacuum (kvac=1), many have developed means to produce voids in the dielectric material. When the void volume extends and occupies substantial contiguous regions of the gaps between the lines one achieves an interconnect structure wherein the lines are nominally separated by air or vacuum as the ILD material. In the following description the term ‘air bridge’ is used to describe such an interconnect structure to distinguish it from structures wherein the ILD is porous with void volume dispersed randomly within a nominally contiguous solid dielectric.
The use of bottom-up approaches to semiconductor fabrication has grown in interest within the scientific community. One such approach utilizes block copolymers for generating sub-optical ground rule patterns. In particular, one illustrative use is forming a ‘honeycomb’ structure, commonly referred to as a hexagonal closed packed structure, within a poly(methyl methacrylate-b-styrene) block copolymer. In the case of a cylindrical phase diblock having a minor component of polymethyl methaerylate (PMMA), the PMMA block can phase separate to form vertically oriented cylinders within the matrix of the polystyrene block upon thermal annealing.
The prior art process of using self-assembled block copolymers includes optionally coating a substrate with a random copolymer. This copolymer is affixed to the surface and excess material is removed. A self-assembled block copolymer is coated on the top surface of the random-substrate stack. The block copolymer is annealed with heat and/or in the presence of solvents, and/or actinic irradiation allowing for phase separation of immiscible polymer blocks. The annealed film is then developed by a suitable method such as immersion in a solvent that dissolves one polymer block and not the other, and reveals a pattern that is commensurate with the positioning of one of the blocks in the copolymer.
Since block copolymers have a natural length scale associated with their molecular weight and composition, the morphology of a phase-separated block copolymer can be tuned to generate cylinders of a specific width and on a specific pitch. Literature shows the use of UV exposure to cause the PMMA to decompose into smaller molecules and, further, developed using glacial acetic acid to remove the small molecules. Others simply develop the acetic acid to reveal a hexagonal close packed (HCP) pattern. A third possible development is using an oxygen plasma, which preferentially etches, for example, PMMA at a higher rate than polystyrene.
One prior art approach to an air bridge construction incorporates the dual damascene and block copolymer technologies mentioned above. Typically, the air bridge is constructed after the metal deposition steps that form the interconnects. For the purpose of reference, these types of processes are designated in the present application as Metal-then-Air Bridge (MAB) approaches consistent with the process sequence used. Most processes that follow this approach begin with the standard dual damascene fabrication sequence. After the metallization step and either before or after the dielectric capped deposition, a nanometer scale pattern is transferred into the underlying interconnect structure and capped with a barrier material. One disadvantage to this prior art approach is the exposure of the metallic lines to a harsh reactive ion etch process that is required for patterning of the interlevel dielectric material.